[CDG5] NanoKernel

Daniel B-J danielbj314 at verizon.net
Tue Dec 4 05:41:06 AWST 2018


Wrote it myself by looking at PowerPC datasheets. The thing is a big mess of code written entirely by me (with a bit of help from StackOverflow and the like).

I guess this is what I get for not reading things close enough. It seems logical instructions have a different operand ordering than arithmetic instructions.

Rather than sending a new version over right away, I think I will wait and see if any more of those bugs pop up.
> On Dec 3, 2018, at 1:59 PM, Max Poliakovski <maximumspatium at googlemail.com> wrote:
> 
> Daniel,
> 
> what disassembler is used using in your dePEF? I noticed that dst and src1 are swapped in some instructions. Below a snippet from the DonnDecompress provided by you:
> 
> .DonnDecompress:
>     mflr r0
>     stmw r21,-0x002c(sp)
>     stw r0, 0x0008(sp)
>     stwu sp,-0x0070(sp)
>     stw r3, 0x0088(sp)
>     addi r22,rtoc, 0x0008
>     or r5,r26,r5 ---> this should be or r26, r5, r5 which corresponds to the simplified form mr r26, r5
>     lwz r23,-0x0004(S_0x1_O_0x4)
>     li r0, 0x0001
>     sth r6, 0x0002(r26)
>     or r4,r31,r4 --> should be or r31, r4, r4
>     sth r0, 0x0000(r26)
> 
> Another snippet:
> 
> S_0x0_O_0x0:
>     lwz r11, 0x0000(r3)
>     lbz r12, 0x0000(r11)
>     addi r10,r11, 0x0001
>     cmplwi cr0, r12, 0x0080
>     bt 0,S_0x0_O_0x68
>     lbz r9, 0x0001(r11)
>     cmpwi cr0, r12, 0x00ff
>     bf 2,S_0x0_O_0x4C
>     lbz r4, 0x0003(r11)
>     rlwinm r9,r0,24,0,7 --> should be rlwinm r0,r9,24,0,7 to make sense
>     lbz r7, 0x0002(r11)
>     rlwinm r4,r4,8,0,23
>     lbz r5, 0x0004(r11)
>     rlwinm r7,r7,16,0,15
>     addi r10,r11, 0x0005
>     add r6,r5,r4
>     add r8,r6,r7
>     add r12,r8,r0
>     b   S_0x0_O_0x68
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