[CDG5] Getting old world ROM boot on QEMU g3beige
BALATON Zoltan
balaton at eik.bme.hu
Fri Jul 3 21:53:27 AWST 2020
Hello,
We've made some progress with getting a Mac ROM boot with QEMU g3beige
machine and thought you might be interested or could give some hints about
what else could be missing to get it working. This currently needs patches
not in upstream repo yet, I have these patches in my branch;
audio: add dummy screamer device
macio: basic AWACS/screamer hookup
screamer: some basic reg work, plus basic DMA wire-up
WIP: basic DMA functionality for screamer
WIP: wire up to new world machine
WIP: screamer now able to play on Debian Linux/snd_powermac
WIP: working sound in MacOS 9.1/9.2
WIP: Add OpenBIOS with screamer support
The above are Mark's screamer patches rebased on master, you should be
able to apply these on master without conflicts. Don't know what's the
best way to do that but I've done something like this:
git clone [qemu master]
git checkout -b macrom #create a new branch for this
git remote add -t screamer --no-tags -f mark https://github.com/mcayland/qemu.git
git rebase mark/screamer
(haven't tested if this actually works) Then on top of that I have my
latest series:
mac_oldworld: Allow loading binary ROM image
mac_newworld: Allow loading binary ROM image
mac_oldworld: Drop a variable, use get_system_memory() directly
mac_oldworld: Drop some variables
mac_oldworld: Change PCI address of macio to match real hardware
i2c: Match parameters of i2c_start_transfer and i2c_send_recv
WIP macio/cuda: Attempt to add i2c support
mac_oldworld: Add SPD data to cover RAM
This can be downloaded from here:
https://patchew.org/QEMU/[email protected]/
You should be able to use "git am" with the mbox downloaded from the
patchew link to get these applied. Then for the Mac ROM a fix to screamer
buffer size is also needed as noted here:
https://lists.nongnu.org/archive/html/qemu-ppc/2020-06/msg00650.html
to avoid crashing QEMU but this only allows you to hear the startup sound
at the moment, the ROM crashes later as shown below.
The firmware ROM seems to expect the GPU to be at PCI address 0x12 and
does not seem to touch other devices. I wonder how does a plug-in PCI
graphics card wotks on real hardware because that's probably a different
PCI address? Maybe it will init on board gfx always before looking for
other PCI devices and if that fails it does not go further or also looks
for plug-in cards at specific PCI addresses the slots are mapped to? I
don't know but we can put the emulated GPU at the expected address and
then the ROM tries to configure it if it's the expected PCI ID of a Rage
Pro Turbo (aka some Mach64 variant). I've tried that with ati-vga changing
only the ID but it's not simliar enough to get picture. The regs it pokes
are not implemented on Rage128Pro so these would need to be added to
emulate the older mach64 based Rage Pro. But I've noticed the firmware ROM
tries to map the card's ROM BAR and would run an FCode ROM from there so
supplying an appropriate driver in there might work for other chips. I've
tried with a ROM from a Rage 128 Pro card that we've experimented with
before to boot MacOS and was known to work to boot MacOS and with that ROM
inits the card and switches mode to 640x480x8, reads EDID info then
enables display but still runs in the same problem as before at the end
wihtout getting something displayed. The command I've used (with all my
and Mark's patces plus some debug defines enabled to get more detailed
logs):
qemu-system-ppc -net none -vga none
-device ati-vga,addr=0x12,romfile=ati-rage128ps.rom -bios 78F57389.rom
-d unimp,guest_errors -trace enable="pci*" -trace enable="i2c*"
-trace enable="cuda*" -trace enable="*ati*" -serial stdio
(Tried also with both rage128pd and rage128ps roms, the PD one seems to
stall longer before reading EDID while the PS is faster but both end in
the same result. I'm getting these logs:
[some less interesting logs at the bginnig were cut from here]
cuda_packet_receive length 3
cuda_packet_receive_data [0] 0x01
cuda_packet_receive_data [1] 0x01
cuda_packet_receive_data [2] 0xff
cuda_receive_packet_cmd handling command AUTOPOLL
cuda_packet_send length 3
cuda_packet_send_data [0] 0x01
cuda_packet_send_data [1] 0x00
cuda_packet_send_data [2] 0x01
cuda_delay_set_sr_int
cuda_data_recv recv: 0x01
cuda_delay_set_sr_int
cuda_data_recv recv: 0x00
cuda_delay_set_sr_int
cuda_data_recv recv: 0x01
cuda_delay_set_sr_int
cuda_delay_set_sr_int
cuda_data_send send: 0x00
cuda_delay_set_sr_int
cuda_data_send send: 0x2f
cuda_delay_set_sr_int
cuda_delay_set_sr_int
cuda_packet_receive length 2
cuda_packet_receive_data [0] 0x00
cuda_packet_receive_data [1] 0x2f
cuda_packet_send length 4
cuda_packet_send_data [0] 0x00
cuda_packet_send_data [1] 0x00
cuda_packet_send_data [2] 0x02
cuda_packet_send_data [3] 0x01
cuda_delay_set_sr_int
cuda_data_recv recv: 0x00
cuda_delay_set_sr_int
cuda_data_recv recv: 0x00
cuda_delay_set_sr_int
cuda_data_recv recv: 0x02
cuda_delay_set_sr_int
cuda_data_recv recv: 0x01
cuda_delay_set_sr_int
cuda_delay_set_sr_int
pci_cfg_read ati-vga 18:0 @0x0 -> 0x50461002
pci_cfg_read ati-vga 18:0 @0xc -> 0x0
pci_cfg_read ati-vga 18:0 @0x0 -> 0x50461002
pci_cfg_read ati-vga 18:0 @0x0 -> 0x50461002
pci_cfg_read ati-vga 18:0 @0x8 -> 0x3000000
pci_cfg_read ati-vga 18:0 @0x3c -> 0x100
pci_cfg_read ati-vga 18:0 @0xc -> 0x0
pci_cfg_read ati-vga 18:0 @0x2c -> 0x11001af4
pci_cfg_read ati-vga 18:0 @0x4 -> 0x0
pci_cfg_read ati-vga 18:0 @0x8 -> 0x3000000
pci_cfg_write ati-vga 18:0 @0xc <- 0x2008
pci_cfg_write ati-vga 18:0 @0x4 <- 0x9c
pci_cfg_read ati-vga 18:0 @0x8 -> 0x3000000
pci_cfg_write ati-vga 18:0 @0x10 <- 0x0
pci_cfg_write ati-vga 18:0 @0x14 <- 0x0
pci_cfg_write ati-vga 18:0 @0x18 <- 0x0
pci_cfg_write ati-vga 18:0 @0x1c <- 0x0
pci_cfg_write ati-vga 18:0 @0x20 <- 0x0
pci_cfg_write ati-vga 18:0 @0x24 <- 0x0
pci_cfg_write ati-vga 18:0 @0x30 <- 0xfffff800
pci_cfg_read ati-vga 18:0 @0x30 -> 0xfffe0000
pci_cfg_write ati-vga 18:0 @0x30 <- 0x80800001
pci_cfg_read ati-vga 18:0 @0x4 -> 0x4
pci_cfg_write ati-vga 18:0 @0x4 <- 0x6
pci_update_mappings_add d=0x559528e54e00 00:12.0 6,0x80800000+0x20000
pci_update_mappings: adding bar 6 to pci-mmio @ 0x80800000
[FCode ROM mapped here by OF]
pci_cfg_read ati-vga 18:0 @0x0 -> 0x50461002
pci_cfg_read ati-vga 18:0 @0x8 -> 0x3000000
pci_cfg_write ati-vga 18:0 @0x14 <- 0xc00
pci_cfg_read ati-vga 18:0 @0x4 -> 0x6
pci_cfg_write ati-vga 18:0 @0x4 <- 0x7
pci_update_mappings_add d=0x559528e54e00 00:12.0 1,0xc00+0x100
pci_update_mappings: adding bar 1 to pci-isa-mmio @ 0xc00
ati_mm_write 4 0x50 CRTC_GEN_CNTL <- 0x5000200
ati_vga_switch_mode: 0 -> 1
ati_mm_write 4 0x30 BUS_CNTL <- 0x71b3a340
ati_mm_write 4 0x34 BUS_CNTL1 <- 0x1f
ati_mm_write 4 0x58 DAC_CNTL <- 0xff000102
ati_mm_write 4 0xf0 GEN_RESET_CNTL <- 0x0
ati_mm_write 4 0x130 unknown <- 0x2044
ati_mm_write 4 0x128 unknown <- 0x690008
ati_mm_write 4 0x16a0 GUI_DEBUG0 <- 0x0
ati_mm_write 4 0x1720 WAIT_UNTIL <- 0x0
ati_mm_write 4 0x180 PC_NGUI_MODE <- 0x122
ati_mm_write 4 0x94 I2C_CNTL_1 <- 0x10000
ati_mm_write 4 0x90 unknown <- 0x10000
ati_mm_write 1 0x8 CLOCK_CNTL_INDEX <- 0x90
[more stuff poking ati-vga regs here, I assume this is the FCode ROM running]
ati_mm_write 4 0x20c CRTC_V_SYNC_STRT_WID <- 0x8301e2
ati_mm_write 4 0x208 CRTC_V_TOTAL_DISP <- 0x1df020c
ati_mm_write 4 0x204 CRTC_H_SYNC_STRT_WID <- 0x8802c0
ati_mm_write 4 0x200 CRTC_H_TOTAL_DISP <- 0x4f006b
ati_mm_write 2 0x50 CRTC_GEN_CNTL <- 0x200
ati_mm_write 1 0xe0 CNFG_CNTL <- 0x0
ati_mm_write 4 0x22c CRTC_PITCH <- 0x60
ati_mm_write 4 0x224 CRTC_OFFSET <- 0x8000
ati_mm_read 1 0x55 CRTC_EXT_CNTL -> 0x0
ati_mm_write 1 0x55 CRTC_EXT_CNTL <- 0x4
ati_mm_write: Display disabled
ati_vga_switch_mode: 1 -> 1
ati_mm_write 4 0x254 unknown <- 0x0
ati_mm_write 4 0x258 unknown <- 0x0
ati_mm_write 4 0x2c4 unknown <- 0x0
ati_mm_write 4 0x2c8 unknown <- 0x0
ati_mm_write 4 0x28c unknown <- 0x0
ati_mm_write 4 0x290 unknown <- 0x0
ati_mm_write 4 0x230 OVR_CLR <- 0x0
ati_mm_write 4 0x234 OVR_WID_LEFT_RIGHT <- 0x0
ati_mm_write 4 0x238 OVR_WID_TOP_BOTTOM <- 0x0
ati_mm_read 4 0x288 unknown -> 0x0
ati_mm_write 4 0x288 unknown <- 0x0
ati_mm_read 4 0x284 unknown -> 0x0
ati_mm_write 4 0x284 unknown <- 0x2
ati_mm_read 4 0x54 CRTC_EXT_CNTL -> 0x400
ati_mm_write 4 0x54 CRTC_EXT_CNTL <- 0x400
ati_mm_write: Display disabled
ati_mm_read 4 0x58 DAC_CNTL -> 0xff000102
ati_mm_write 4 0x58 DAC_CNTL <- 0xff000102
ati_mm_write 1 0x53 CRTC_GEN_CNTL <- 0x3
ati_vga_switch_mode: 1 -> 1
ati_vga_switch_mode: Switching to 640x480 768 8 @ 8000
ati_vga_switch_mode: CRTC offset is not multiple of pitch
ati_vga_switch_mode: VBE offset (512,42), vbe_start_addr=2000
[Display mode is swithed here but display is not yet enabled, it stops
here for a while, I don't know what it's doing here, may have a sleep here
for card to stabilise or relies on something we don't emulate? This takes
longer with PD rom. I get no logs here just CPU spins until it starts
reading EDID:]
bitbang_i2c: STOP
bitbang_i2c: STOP
bitbang_i2c: STOP
bitbang_i2c: START
bitbang_i2c: Address 0xa0
i2c_event start(addr:0x50)
bitbang_i2c: Sent 0x00
i2c_send send(addr:0x50) data:0x00
i2c-ddc: [EDID] Written new pointer: 0
bitbang_i2c: STOP
i2c_event finish(addr:0x50)
bitbang_i2c: START
bitbang_i2c: Address 0xa1
i2c_event start(addr:0x50)
i2c_recv recv(addr:0x50) data:0x00
bitbang_i2c: RX byte 0x00
bitbang_i2c: ACKED
i2c_recv recv(addr:0x50) data:0xff
bitbang_i2c: RX byte 0xff
bitbang_i2c: ACKED
i2c_recv recv(addr:0x50) data:0xff
[Reads EDID data here then programs mode; I haven't checked but sync
values look suspicious so we may have something wrong in EDID but we
ignore these sync values anyway so unless it confuses ROM it's probably OK
and it has worked before in OpenBIOS with my patches with same ati-vga so
hopefully it's not a problem but not completely sure]
i2c_recv recv(addr:0x50) data:0x00
bitbang_i2c: RX byte 0x00
bitbang_i2c: ACKED
i2c_recv recv(addr:0x50) data:0x33
bitbang_i2c: RX byte 0x33
bitbang_i2c: ACKED
bitbang_i2c: STOP
i2c_event finish(addr:0x50)
ati_mm_read 1 0x20e CRTC_V_SYNC_STRT_WID -> 0x0
ati_mm_write 1 0x20e CRTC_V_SYNC_STRT_WID <- 0x0
ati_mm_write 1 0x20e CRTC_V_SYNC_STRT_WID <- 0x80
ati_mm_write 1 0x20e CRTC_V_SYNC_STRT_WID <- 0x0
ati_mm_write 1 0x53 CRTC_GEN_CNTL <- 0x5
ati_vga_switch_mode: 1 -> 1
ati_mm_write 1 0x8 CLOCK_CNTL_INDEX <- 0x89
ati_mm_write 4 0xc CLOCK_CNTL_DATA <- 0x0
ati_mm_write 4 0x28c unknown <- 0x0
ati_mm_write 4 0x290 unknown <- 0x0
ati_mm_read 1 0x55 CRTC_EXT_CNTL -> 0x4
ati_mm_write 1 0x55 CRTC_EXT_CNTL <- 0x0
ati_mm_write: Display enabled
ati_vga_switch_mode: 1 -> 1
ati_vga_switch_mode: 1 -> 1
[Display is enabled here but it's blank yet should now draw something in
it which needs VRAM BAR mapped]
ati_mm_read 1 0x58 DAC_CNTL -> 0xff000102
ati_mm_write 1 0x58 DAC_CNTL <- 0xa
ati_mm_write 4 0x230 OVR_CLR <- 0x525252
ati_mm_read 1 0x58 DAC_CNTL -> 0xa
ati_mm_write 4 0x230 OVR_CLR <- 0x0
ati_mm_write 1 0x58 DAC_CNTL <- 0x2
ati_mm_write 4 0x284 unknown <- 0xa
ati_mm_write 4 0x288 unknown <- 0xff00
ati_mm_read 4 0x2a4 unknown -> 0x0
ati_mm_write 4 0x2a4 unknown <- 0x1
ati_mm_write 4 0x2a4 unknown <- 0x1
ati_mm_write 4 0x2a8 unknown <- 0x99c
ati_mm_write 4 0x294 unknown <- 0x1000000
pci_cfg_read ati-vga 18:0 @0x4 -> 0x7
pci_cfg_write ati-vga 18:0 @0x4 <- 0x6
pci_update_mappings_del d=0x559528e54e00 00:12.0 1,0xc00+0x100
pci_update_mappings: removing bar 1 from pci-isa-mmio
pci_cfg_read ati-vga 18:0 @0x10 -> 0x8
pci_cfg_write ati-vga 18:0 @0x30 <- 0x0
pci_update_mappings_del d=0x559528e54e00 00:12.0 6,0x80800000+0x20000
pci_update_mappings: removing bar 6 from pci-mmio
[Unmaps BARs here. Is it finished or it expected some value from one of
the not emulated regs and exited with error?]
pci_cfg_read ati-vga 18:0 @0x4 -> 0x6
pci_cfg_write ati-vga 18:0 @0x4 <- 0x4
pci_cfg_write ati-vga 18:0 @0x18 <- 0x80800000
pci_cfg_write ati-vga 18:0 @0x30 <- 0x80820000
pci_cfg_write ati-vga 18:0 @0x10 <- 0x84000000
[It seems to write BARs here including BAR0 which is the framebuffer VRAM
but it's not mapped (memory bit not set in command reg @0x4). What's
happening here? I think this should set up framebuffer memory at this
point and the reason we don't see a picture is that these BARs remain
unmapped.]
pci_cfg_read grackle 00:0 @0x3c -> 0x0
pci_cfg_read grackle 00:0 @0x3c -> 0x0
pci_cfg_write grackle 00:0 @0x3f <- 0x0
pci_cfg_write grackle 00:0 @0x3c <- 0x0
pci_cfg_write grackle 00:0 @0x3d <- 0x0
pci_cfg_write grackle 00:0 @0x3e <- 0x0
cuda_data_send send: 0x00
cuda_delay_set_sr_int
cuda_data_send send: 0x00
cuda_delay_set_sr_int
cuda_delay_set_sr_int
cuda_packet_receive length 2
cuda_packet_receive_data [0] 0x00
cuda_packet_receive_data [1] 0x00
cuda_packet_send length 3
cuda_packet_send_data [0] 0x00
cuda_packet_send_data [1] 0x00
cuda_packet_send_data [2] 0x00
cuda_delay_set_sr_int
[Don't know what the grackle regs are and is this all 0 CUDA packet normal
or it's already wrong here?]
Unassigned mem read 000000000fefe7b0
Unassigned mem write 000000000feffffc = 0x0
Unassigned mem write 000000000feffff8 = 0x0
Unassigned mem write 000000000feffff4 = 0x0
Unassigned mem write 000000000feffff0 = 0x0
[Then it fills up this unmapped area, I think this should be writing the
frame buffer RAM which should be somewhere in 0x84000000 if the above
worked. What's wrong here? This goes on until 0x0febe000, then:]
Unassigned mem write 000000000febe010 = 0x0
Unassigned mem write 000000000febe00c = 0x0
Unassigned mem write 000000000febe008 = 0x0
Unassigned mem write 000000000febe004 = 0x0
Unassigned mem write 000000000febe000 = 0x0
Unassigned mem write 000000000fefe908 = 0x0
Unassigned mem write 000000000fefe90c = 0x0
Unassigned mem write 000000000fefefbc = 0x0
Unassigned mem write 000000000fefefb8 = 0x0
Unassigned mem write 000000000fefefb4 = 0x0
Unassigned mem write 000000000fefefb0 = 0x0
Unassigned mem write 000000000fefefac = 0x0
Unassigned mem write 000000000fefefa8 = 0x0
Unassigned mem write 000000000fefefa4 = 0x20000
Unassigned mem write 000000000fefefa0 = 0x2
Unassigned mem write 000000000fefef9c = 0x10000
Unassigned mem write 000000000fefef98 = 0x0
Unassigned mem write 000000000fefef94 = 0x0
Unassigned mem write 000000000fefef90 = 0x0
Unassigned mem write 000000000fefef8c = 0x0
Unassigned mem write 000000000fefef88 = 0x0
Unassigned mem write 000000000fefef84 = 0x0
Unassigned mem write 000000000fefef80 = 0x0
Unassigned mem write 000000000fefef7c = 0x0
Unassigned mem write 000000000fefef78 = 0x0
Unassigned mem write 000000000fefef74 = 0x0
Unassigned mem write 000000000fefef70 = 0x0
Unassigned mem write 000000000fefef6c = 0xbebc20
Unassigned mem write 000000000fefef68 = 0x2faf080
Unassigned mem write 000000000fefef64 = 0x2faf080
Unassigned mem write 000000000fefef60 = 0x0
Unassigned mem write 000000000fefed5c = 0x0
Unassigned mem write 000000000fefed58 = 0x0
Unassigned mem write 000000000fefed54 = 0x0
Unassigned mem write 000000000fefed50 = 0x0
Unassigned mem write 000000000fefed4c = 0x0
Unassigned mem write 000000000fefed48 = 0x0
Unassigned mem write 000000000fefed44 = 0x0
Unassigned mem write 000000000fefed40 = 0x0
Unassigned mem write 000000000fefed3c = 0x0
Unassigned mem write 000000000fefed38 = 0x0
Unassigned mem write 000000000fefed34 = 0x0
Unassigned mem write 000000000fefed30 = 0x0
Unassigned mem write 000000000fefed2c = 0x0
Unassigned mem write 000000000fefed28 = 0x0
Unassigned mem write 000000000fefed24 = 0x0
Unassigned mem write 000000000fefed20 = 0x0
Unassigned mem write 000000000fefed1c = 0x0
Unassigned mem write 000000000fefed18 = 0x0
Unassigned mem write 000000000fefed14 = 0x0
Unassigned mem write 000000000fefed10 = 0x0
Unassigned mem write 000000000fefed0c = 0x0
Unassigned mem write 000000000fefed08 = 0x0
Unassigned mem write 000000000fefed04 = 0x0
Unassigned mem write 000000000fefed00 = 0x0
Unassigned mem write 000000000fefecfc = 0x0
Unassigned mem write 000000000fefecf8 = 0x0
Unassigned mem write 000000000fefecf4 = 0x0
Unassigned mem write 000000000fefecf0 = 0x0
Unassigned mem write 000000000fefecec = 0x0
Unassigned mem write 000000000fefece8 = 0x0
Unassigned mem write 000000000fefece4 = 0x0
Unassigned mem write 000000000fefece0 = 0x0
Unassigned mem write 000000000fefecdc = 0x0
Unassigned mem write 000000000fefecd8 = 0x0
Unassigned mem write 000000000fefecd4 = 0x0
Unassigned mem write 000000000fefecd0 = 0x0
Unassigned mem write 000000000fefeccc = 0x0
Unassigned mem write 000000000fefecc8 = 0x0
Unassigned mem write 000000000fefecc4 = 0x0
Unassigned mem write 000000000fefecc0 = 0x0
Unassigned mem write 000000000fefecbc = 0x0
Unassigned mem write 000000000fefecb8 = 0x0
Unassigned mem write 000000000fefecb4 = 0x0
Unassigned mem write 000000000fefecb0 = 0x0
Unassigned mem write 000000000fefecac = 0x0
Unassigned mem write 000000000fefeca8 = 0x0
Unassigned mem write 000000000fefeca4 = 0x0
Unassigned mem write 000000000fefeca0 = 0x0
Unassigned mem write 000000000fefec9c = 0x0
Unassigned mem write 000000000fefec98 = 0x0
Unassigned mem write 000000000fefec94 = 0x0
Unassigned mem write 000000000fefec90 = 0x0
Unassigned mem write 000000000fefec8c = 0x0
Unassigned mem write 000000000fefec88 = 0x0
Unassigned mem write 000000000fefec84 = 0x0
Unassigned mem write 000000000fefec80 = 0x0
Unassigned mem write 000000000fefec7c = 0x8000000
Unassigned mem write 000000000fefec78 = 0x8000000
Unassigned mem write 000000000fefec74 = 0x8000000
Unassigned mem write 000000000fefec70 = 0x0
Unassigned mem write 000000000fefec6c = 0x0
Unassigned mem write 000000000fefec68 = 0x0
Unassigned mem write 000000000fefec64 = 0x0
Unassigned mem write 000000000fefec60 = 0x20000
Unassigned mem write 000000000fefec5c = 0x200002
Unassigned mem write 000000000fefec58 = 0x10020
Unassigned mem write 000000000fefec54 = 0x4
Unassigned mem write 000000000fefec50 = 0x4
Unassigned mem write 000000000fefec4c = 0x0
Unassigned mem write 000000000fefec48 = 0x0
Unassigned mem write 000000000fefec44 = 0x0
Unassigned mem write 000000000fefec40 = 0x10000000
Unassigned mem write 000000000fefee5c = 0x0
Unassigned mem write 000000000fefee58 = 0x0
Unassigned mem write 000000000fefee54 = 0x0
Unassigned mem write 000000000fefee50 = 0x0
Unassigned mem write 000000000fefee4c = 0x0
Unassigned mem write 000000000fefee48 = 0x0
Unassigned mem write 000000000fefee44 = 0x0
Unassigned mem write 000000000fefee40 = 0x0
Unassigned mem write 000000000fefee3c = 0x0
Unassigned mem write 000000000fefee38 = 0x0
Unassigned mem write 000000000fefee34 = 0x0
Unassigned mem write 000000000fefee30 = 0x0
Unassigned mem write 000000000fefee2c = 0x0
Unassigned mem write 000000000fefee28 = 0x0
Unassigned mem write 000000000fefee24 = 0x0
Unassigned mem write 000000000fefee20 = 0x0
Unassigned mem write 000000000fefee1c = 0x0
Unassigned mem write 000000000fefee18 = 0x0
Unassigned mem write 000000000fefee14 = 0x0
Unassigned mem write 000000000fefee10 = 0x0
Unassigned mem write 000000000fefee0c = 0x0
Unassigned mem write 000000000fefee08 = 0x0
Unassigned mem write 000000000fefee04 = 0x0
Unassigned mem write 000000000fefee00 = 0x0
Unassigned mem write 000000000fefedfc = 0x0
Unassigned mem write 000000000fefedf8 = 0x0
Unassigned mem write 000000000fefedf4 = 0x0
Unassigned mem write 000000000fefedf0 = 0x0
Unassigned mem write 000000000fefedec = 0x0
Unassigned mem write 000000000fefede8 = 0x0
Unassigned mem write 000000000fefede4 = 0x0
Unassigned mem write 000000000fefede0 = 0x0
Unassigned mem write 000000000fefeddc = 0x0
Unassigned mem write 000000000fefedd8 = 0x0
Unassigned mem write 000000000fefedd4 = 0x0
Unassigned mem write 000000000fefedd0 = 0x0
Unassigned mem write 000000000fefedcc = 0x0
Unassigned mem write 000000000fefedc8 = 0x0
Unassigned mem write 000000000fefedc4 = 0x0
Unassigned mem write 000000000fefedc0 = 0x0
Unassigned mem write 000000000fefedbc = 0x0
Unassigned mem write 000000000fefedb8 = 0x0
Unassigned mem write 000000000fefedb4 = 0x0
Unassigned mem write 000000000fefedb0 = 0x0
Unassigned mem write 000000000fefedac = 0x0
Unassigned mem write 000000000fefeda8 = 0x0
Unassigned mem write 000000000fefeda4 = 0x0
Unassigned mem write 000000000fefeda0 = 0x0
Unassigned mem write 000000000fefed9c = 0x0
Unassigned mem write 000000000fefed98 = 0x0
Unassigned mem write 000000000fefed94 = 0x0
Unassigned mem write 000000000fefed90 = 0x0
Unassigned mem write 000000000fefed8c = 0x0
Unassigned mem write 000000000fefed88 = 0x0
Unassigned mem write 000000000fefed84 = 0x0
Unassigned mem write 000000000fefed80 = 0x0
Unassigned mem write 000000000fefed7c = 0x0
Unassigned mem write 000000000fefed78 = 0x0
Unassigned mem write 000000000fefed74 = 0x0
Unassigned mem write 000000000fefed70 = 0x0
Unassigned mem write 000000000fefed6c = 0x0
Unassigned mem write 000000000fefed68 = 0x0
Unassigned mem write 000000000fefed64 = 0x0
Unassigned mem write 000000000fefed60 = 0x0
Unassigned mem write 000000000fefe630 = 0xfff0d000
Unassigned mem write 000000000fefe5b0 = 0xfff16880
Unassigned mem write 000000000fefec4c = 0x100000
Unassigned mem write 000000000fefe634 = 0xfeff000
Unassigned mem write 000000000fefe638 = 0xfebe000
Unassigned mem write 000000000fefe63c = 0x10000000
Unassigned mem write 000000000fefe640 = 0x0
Unassigned mem write 000000000fefe644 = 0x0
Unassigned mem write 000000000fefe648 = 0x6806e740
Unassigned mem write 000000000fefe64c = 0xfff10000
Unassigned mem write 000000000fefe650 = 0xfff11400
Unassigned mem write 000000000fefe654 = 0x68fff100
Unassigned mem write 000000000fefe658 = 0xfeff100
Unassigned mem write 000000000fefe65c = 0xfeff100
Unassigned mem write 000000000fefe670 = 0x200000
Unassigned mem write 000000000fefe678 = 0xff9fffff
Unassigned mem write 000000000fefe674 = 0xe00000
Unassigned mem write 000000000fefe67c = 0xfeff070
Unassigned mem write 000000000fefe680 = 0x7c
Unassigned mem write 000000000fefe688 = 0x12
Unassigned mem write 000000000fefe684 = 0xfefe920
Unassigned mem write 000000000fefe66c = 0xfefeab8
Unassigned mem write 000000000fefe910 = 0x0
Unassigned mem write 000000000fefefc0 = 0x5fffefc0
Unassigned mem write 000000000fefefc4 = 0x0
Unassigned mem write 000000000fefefc8 = 0x5fffeb20
Unassigned mem write 000000000fefefcc = 0x100
Unassigned mem write 000000000fefefce = 0x80
Unassigned mem write 000000000fefefd0 = 0x5fffeba0
Unassigned mem write 000000000fefefd4 = 0x102
Unassigned mem write 000000000fefefd6 = 0xa0
Unassigned mem write 000000000fefefd8 = 0x5fffef60
Unassigned mem write 000000000fefefdc = 0x101
Unassigned mem write 000000000fefefde = 0x60
Unassigned mem write 000000000fefefe0 = 0x5fffee60
Unassigned mem write 000000000fefefe4 = 0x101
Unassigned mem write 000000000fefefe6 = 0x100
Unassigned mem write 000000000fefefe8 = 0x5fffed60
Unassigned mem write 000000000fefefec = 0x100
Unassigned mem write 000000000fefefee = 0x100
Unassigned mem write 000000000fefeff0 = 0x5fffec40
Unassigned mem write 000000000fefeff4 = 0x105
Unassigned mem write 000000000fefeff6 = 0x120
Unassigned mem write 000000000fefeff8 = 0x5fffef60
Unassigned mem write 000000000fefeffc = 0x101
Unassigned mem write 000000000fefeffe = 0x60
Unassigned mem write 000000000fefff00 = 0x426f6f74
Unassigned mem write 000000000fefff04 = 0x20476f73
Unassigned mem write 000000000fefff08 = 0x73616d65
Unassigned mem write 000000000fefff0c = 0x7220302e
Unassigned mem write 000000000feff184 = 0x6806e6f4
Unassigned mem write 000000000feff194 = 0x68fff000
Unassigned mem write 000000000feff19c = 0x68080000
Unassigned mem read 000000000fefe648
Unassigned mem write 000000000feff15c = 0x0
Unassigned mem read 000000000fefe640
Unassigned mem read 000000000fefe640
Unassigned mem read 000000000fefec10
Unassigned mem write 000000000fefef60 = 0x80301
Unassigned mem read 000000000fefe64c
Unassigned mem write 000000000fefef90 = 0x0
Unassigned mem write 000000000fefef8c = 0x0
Unassigned mem write 000000000fefef88 = 0x0
Unassigned mem write 000000000fefef84 = 0x0
Unassigned mem write 000000000fefef80 = 0x0
Unassigned mem write 000000000fefef7c = 0x0
Unassigned mem write 000000000fefef78 = 0x0
Unassigned mem write 000000000fefef74 = 0x0
Unassigned mem write 000000000fefef70 = 0x0
Trying to write invalid spr 0 (0x000) at fff10d38
Unassigned mem read 000000000fefe64c
Unassigned mem write 000000000fefe37c = 0x44e0
Unassigned mem read 000000000fefe37c
invalid/unsupported opcode: 00 - 00 - 00 - 00 (00000000) 00000000 0
Unassigned mem read 000000000fefe37c
Unassigned mem read 000000000fefe37c
Unassigned mem read 000000000fefe37c
Unassigned mem read 000000000fefe37c
Unassigned mem read 000000000fefe37c
Unassigned mem read 000000000fefe37c
Unassigned mem read 000000000fefe37c
Unassigned mem read 000000000fefe37c
Then it stops here infinitely reading the above address. The above values
should either go to some device or to the VRAM but it seems these are not
mapped and it writes them at the wrong address so probably we return
something somewhere that confuses it. Any idea anyone what could it be?
I've also tried to get some output from OpenFirmware on serial and added:
-prom-env 'output-device=scca' -prom-env 'input-device=scca' -prom-env 'fcode-debug?=true'
But this did not produce anything, either it's not yet reading these
values (could be -prom-env only works with OpenBIOS?) or there's some
other problem. Also tried adding the grackle revision and machine ID reg
patches to see if they make a difference but got the same results. Any
other ideas where to go from here?
Regards,
BALATON Zoltan
More information about the cdg5
mailing list